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Espressif Systems /ESP32-S2 /APB_SARADC /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADC2_THRES_INT_CLR)ADC2_THRES_INT_CLR 0 (ADC1_THRES_INT_CLR)ADC1_THRES_INT_CLR 0 (ADC2_DONE_INT_CLR)ADC2_DONE_INT_CLR 0 (ADC1_DONE_INT_CLR)ADC1_DONE_INT_CLR

Description

Clear DIG ADC interrupts

Fields

ADC2_THRES_INT_CLR

Clear bit of APB_SARADC_ADC2_THRES_INT interrupt.
ADC1_THRES_INT_CLR

Clear bit of APB_SARADC_ADC1_THRES_INT interrupt.
ADC2_DONE_INT_CLR

Clear bit of APB_SARADC_ADC2_DONE_INT interrupt.
ADC1_DONE_INT_CLR

Clear bit of APB_SARADC_ADC1_DONE_INT interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd